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DM74LS169A Synchronous 4-Bit Up/Down Binary Counter
August 1986 Revised April 2000
DM74LS169A Synchronous 4-Bit Up/Down Binary Counter
General Description
This synchronous presettable counter features an internal carry look-ahead for cascading in high-speed counting applications. Synchronous operation is provided by having all flip-flops clocked simultaneously, so that the outputs all change at the same time when so instructed by the countenable inputs and internal gating. This mode of operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple clock) counters. A buffered clock input triggers the four masterslave flip-flops on the rising edge of the clock waveform. This counter is fully programmable; that is, the outputs may each be preset either HIGH or LOW. The load input circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse. The carry look-ahead circuitry permits cascading counters for n-bit synchronous applications without additional gating. Both count-enable inputs (P and T) must be LOW to count. The direction of the count is determined by the level of the UP/DOWN input. When the input is HIGH, the counter counts UP; when LOW, it counts DOWN. Input T is fed forward to enable the carry outputs. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the high portion of the QA output when counting UP, and approximately equal to the low portion of the QA output when counting DOWN. This lowlevel overflow carry pulse can be used to enable successively cascaded stages. Transitions at the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diode clamped to minimize transmission-line effects, thereby simplifying system design. This counter features a fully independent clock circuit. Changes at control inputs (enable P, enable T, load, UP/ DOWN), which modify the operating mode, have no effect until clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely by the conditions meeting the stable setup and hold times.
Features
s Fully synchronous operation for counting and programming. s Internal look-ahead for fast counting. s Carry output for n-bit cascading. s Fully independent clock circuit
Ordering Code:
Order Number DM74LS169AM DM74LS169AN Package Number M16A N16E Package Description 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Devices also available in Tape and Reel. Specify by appending the suffix letter "X" to the ordering code.
Connection Diagram
(c) 2000 Fairchild Semiconductor Corporation
DS006401
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DM74LS169A
Logic Diagram
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DM74LS169A
Timing Diagram
Typical Load, Count, and Inhibit Sequences
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DM74LS169A
Absolute Maximum Ratings(Note 1)
Supply Voltage Input Voltage Operating Free Air Temperature Range Storage Temperature Range 7V 7V 0C to +70C -65C to +150C
Note 1: The "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The "Recommended Operating Conditions" table will define the conditions for actual device operation.
Recommended Operating Conditions
Symbol VCC VIH VIL IOH IOL fCLK tW tSU Supply Voltage HIGH Level Input Voltage LOW Level Input Voltage HIGH Level Output Current LOW Level Output Current Clock Frequency (Note 2) Clock Frequency (Note 3) Clock Pulse Width (Note 4) Setup Time (Note 4) Data Enable T or P Load U/D tH TA Hold Time (Note 4) Free Air Operating Temperature 0 0 25 20 20 25 30 0 0 70 ns C ns Parameter Min 4.75 2 0.8 -0.4 8 25 20 Nom 5 Max 5.25 Units V V V mA mA MHz MHz ns
Note 2: CL = 15 pF, R L = 2 k, TA = 25C and VCC = 5V. Note 3: CL = 50 pF, R L = 2 k, TA = 25C and VCC = 5V. Note 4: TA = 25C and V CC = 5V.
Electrical Characteristics
over recommended operating free air temperature range (unless otherwise noted) Symbol VI VOH VOL Parameter Input Clamp Voltage HIGH Level Output Voltage LOW Level Output Voltage Conditions VCC = Min, II = -18 mA VCC = Min, IOH = Max VIL = Max, VIH = Min VCC = Min, IOL = Max VIL = Max, VIH = Min IOL = 4 mA, VCC = Min II IIH IIL IOS ICC Input Current @ Max Input Voltage HIGH Level Input Current LOW Level Input Current Short Circuit Output Current Supply Current VCC = Max VI = 7V VCC = Max VI = 2.7V VCC = Max VI = 0.4V VCC = Max (Note 6) VCC = Max (Note 7) Enable T Others Enable T Others Enable T Others -20 20 2.7 3.4 0.35 0.25 0.5 0.4 0.2 0.1 40 20 -0.8 -0.4 -100 34 mA A mA mA mA Min Typ (Note 5) Max -1.5 Units V V
V
Note 5: All typicals are at VCC = 5V and TA = 25C. Note 6: Not more than one output should be shorted at a time, and the duration should not exceed one second. Note 7: ICC is measured after a momentary 4.5V, then ground, is applied to the CLOCK with all other inputs grounded and all the outputs OPEN.
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DM74LS169A
Switching Characteristic
at VCC = 5V and TA = 25C From (Input) Symbol Parameter To (Output) CL = 15 pF Min fMAX tPLH tPHL tPLH tPHL tPLH tPHL tPLH tPHL Maximum Clock Frequency Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Propagation Delay Time LOW-to-HIGH Level Output Propagation Delay Time HIGH-to-LOW Level Output Clock to Ripple Carry Clock to Ripple Carry Clock to Any Q Clock to Any Q Enable T to Ripple Carry Enable T to Ripple Carry Up/Down to Ripple Carry (Note 8) Up/Down to Ripple Carry (Note 8) 25 35 35 20 23 Max RL = 2 k CL = 50 pF Min 20 39 44 24 32 Max MHz ns ns ns ns Units
18
24
ns
18 25 29
28 30 38
ns ns ns
Note 8: The propagation delay from UP/DOWN to RIPPLE CARRY must be measured with the counter at either a minimum or a maximum count. As the logic level of the UP/DOWN input is changed, the ripple carry output will follow. If the count is minimum, the RIPPLE CARRY output transition will be in phase. If the count is maximum, the RIPPLE CARRY output will be out of phase.
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DM74LS169A
Physical Dimensions inches (millimeters) unless otherwise noted
16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A
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DM74LS169A Synchronous 4-Bit Up/Down Binary Counter
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. 7 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com
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